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PIC32MX3XX/4XX
13.0
TIMER1
This family of PIC32MX devices features one
synchronous/asynchronous 16-bit timer that can oper-
Note 1: This data sheet summarizes the features of
the PIC32MX3XX/4XX family of devices.
It is not intended to be a comprehensive
reference source. To complement the
information in this data sheet, refer to
ate as a free-running interval timer for various timing
applications and counting external events. This timer
can also be used with the Secondary Oscillator (S OSC )
for real-time clock applications. The following modes
are supported:
Section 14. “Timers” (DS61105) of the
“PIC32MX Family Reference Manual” ,
which is available from the Microchip web
site (www.microchip.com/PIC32).
2: Some registers and associated bits
?
?
?
?
Synchronous Internal Timer
Synchronous Internal Gated Timer
Synchronous External Timer
Asynchronous External Timer
described in this section may not be avail-
13.1
Additional Supported Features
“Memory Organization” in this data
sheet for device-specific register and bit
information.
? Selectable clock prescaler
? Timer operation during CPU Idle and Sleep mode
? Fast bit manipulation using CLR, SET and INV
registers
? Asynchronous mode can be used with the S OSC
to function as a Real-Time Clock (RTC)
FIGURE 13-1:
TIMER1 BLOCK DIAGRAM (1)
PR1
Equal
Reset
16-bit Comparator
TMR1
TSYNC (T1CON<2>)
Sync
1
0
T1IF
Event Flag
0
1
TGATE (T1CON<7>)
Q
Q
D
TGATE (T1CON<7>)
TCS (T1CON<1>)
ON (T1CON<15>)
SOSCO/T1CK
x1
SOSCI
SOSCEN
Gate
Sync
PBCLK
10
00
Prescaler
1, 8, 64, 256
2
TCKPS<1:0>
(T1CON<5:4>)
Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word DEVCFG1.
? 2010 Microchip Technology Inc.
DS61143G-page 103
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